Modern integrated circuit technology relies on transistors and memory cells to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors and memory cells. As the number of transistors and memory cells required increases, the surface area that can be dedicated to a single component dwindles. Today, also, high reliability is needed in each component to reduce the amount of redundancy needed to guarantee proper operation. Additionally, it is desired to have uniformity among memory cells to facilitate uniform erasure and avoid charge leakage for such memory devices. Thus, it is desirable to construct integrated circuit components which have higher reliability and greater uniformity that can accommodate higher density arrangement on the surface of the silicon chip.
Non volatile floating gate tunneling oxide (FLOTOX) devices, i.e. FLOTOX transistors, offer the prospect of very high density memory cell structures. Flash memories are one form of FLOTOX devices and electronically erasable and programmable read only memories (EEPROMs) are another. Due to their high density nature, memories formed with FLOTOX transistors have the potential of replacing hard storage disk drives in computer systems. The advantages to this substitution would be in replacing a complex and delicate mechanical system with a rugged and easily portable small solid-state non-volatile memory system. There is also the possibility that given more speed of operation, particularly in the erase operation, that FLOTOX transistors might be used to replace dynamic random access memories (DRAMs). Thus, FLOTOX transistors might eventually have the ability to fill all memory needs in future computer systems.
In operation, FLOTOX transistors can be electronically programmed, erased, and reprogrammed. In FLOTOX transistors a floating gate is electrically isolated and any charge stored on the floating gate is trapped. Storing sufficient charge on the floating gate will make it more difficult to form an inversion channel between the source and drain of the FLOTOX transistor. Thus, the presence or absence of charge on the floating gate represents two distinct data states.
Typically, FLOTOX transistors are selectively programmed, or “written to,” by hot electron injection which places a charge on a floating gate during a write. The FLOTOX transistors are selectively erased by Fowler-Nordheim tunneling which removes the charge from the floating gate. During a write, a high programming voltage is placed on a control gate. This forces an inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage while the source is grounded, increasing the voltage drop between the drain and source. In the presence of the inversion region, the current between the drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the outside barrier and collect on the floating gate.
After the write is completed, the negative charge on the floating gate raises the transistor's threshold voltage (VT) above the wordline logic 1 voltage. When a written transistor's wordline is brought to a logic 1 during a read, the transistors will not turn on. Sense amplifiers detect and amplify the transistor current, and output a logic 0 for a written transistor.
The floating gate can be unprogrammed, or “erased,” by grounding the control gate and raising the source voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the source terminal of the transistor by tunneling through the insulating gate oxide. After the erase is completed, the lack of charge on the floating gate lowers the cell's VT below the wordline logic 1 voltage. Thus when an erased cell's wordline is brought to a logic 1 during a read, the transistor will turn on and conduct more current than a written cell. Some flash devices use Fowler-Nordheim tunneling for write as well as erase.
One of the present hurdles in reducing the size of the FLOTOX transistor is related to the creation of the floating polysilicon gate and the shallow trench isolation region between adjacent FLOTOX transistors. Typically, the shallow trench isolation and the floating polysilicon gate are defined using two different lithography masks. Because of potential errors in the alignment of these two layers, the cell design must include extra area for the overlap of the floating polysilicon gate with the shallow trench isolation. In addition, the process steps required to form the shallow trench isolation, along with the processing steps between the formation of the shallow trench isolation region and the growth of the tunnel oxide/deposition of the floating polysilicon gate, create the potential for the thinning of the tunnel oxide.
Thinning of the tunnel oxide can lead to at least two performance problems. A first problem is erase uniformity. Flash memory is not erased on a cell by cell basis, but rather on a block by block basis. Because a large number of cells are erased at the same time, it is important that all of the cells within each block erase at close to the same rate. Any variation in field edge thinning will increase the cell to cell erase distribution. A second problem is data retention. The thinning of the tunnel oxide, at the field edges, can create localized tunneling at the these regions. Because of the higher fields and density of charge during erase, in these regions, long term data retention can become a problem.
Another problem arises when the device size is reduced, the gate coupling ratio (GCR) decreases. The surface area of the two gates is reduced when the overall size of the device is reduced. The GCR is a factor of the surface area of the two gates and is thereby decreased as the surface area of the gates diminishes. In order to overcome this loss in GCR, the periphery transistors must operate at higher voltage levels. If the loss of gate coupling is large enough, this may require the periphery transistors to operatate near their breakdown levels.
One method used to recover surface area lost as the overall device size is reduced is described in “A Novel High-Density 5F2 NAND STI Cell Technology Suitable for 256 Mbit and 1 Gbit Flash Memories”, K. Shimizu, K. Narita, H. Watanabe, E. Kamiya, T. Yaegashi, S. Aritome and T. Watanabe, 1997 IEDM 271–274. The method used was to 1) deposit a second polysilicon layer over the first polysilicon film, 2) a thin layer of silicon-nitride is then deposited over the second polysilicon layer, 3) a lithography level is then used to pattern the silicon nitride film only, 4) a second layer of silicon nitride is then deposited over the patterned silicon nitride film, 5) the second layer of silicon nitride next receives a blanket directional etch to form 2nd layer silicon nitride spacers on the patterned edges of the 1st layer of silicon nitride, 6) the final silicon nitride structure is than used as an etch mask to etch/remove the second polysilicon film over the shallow trench isolation, and 7) the silicon nitride mask is removed. The final outcome of all of the above processing is the addition of an extension over a certain percent of the shallow trench isolation. This process allows for very small gaps between the floating polysilicon gate, cell to cell. This leads to an increase in surface area between the floating gate and the control gate, with no increase in surface area between floating gate and the silicon substrate. The net result is increased coupling of the control gate to the floating gate. The problem with this approach is that the process becomes very complex. The process requires two additional silicon-nitride depositions, one additional lithography step, two additional silicon-nitride etch steps, one additional polysilicon etch step and finally the removal of the silicon-nitride mask.
Thus, what is needed is a method and apparatus for creating integrated circuit components which have higher reliability and greater uniformity and that can accommodate a higher density arrangement on the surface of the silicon chip without a loss in gate coupling ratio and with a simplified fabrication process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop a method and structure for improved FLOTOX transistors.